Plenary Talks
Prof. Ching-Ting Lee (National Cheng Kung University / Yuan Ze University)
Integrated Electronics using GaN-based Complementary Enhancement Mode and Depletion Mode Metal-Oxide-Semiconductor High-Electron Mobility Transistors
Gallium nitride (GaN)-based semiconductors have become promising candidate for the high frequency and high power operation Integrated Circuits (ICs) due to their high breakdown voltage, high speed and high power performances. To achieve the high power operation and handling capability, the conventional Schottky gate structure was replaced by using the metal-oxide-semiconductor structure to fabricate GaN-based devices. In this research, AlGaN/GaN-based structure was used to fabricate complementary metal-oxide-semiconductor high electron mobility transistors (CMOS-HEMTs) composed of an enhancement mode (E-mode) and a depletion mode (D-mode) HEMT devices. In the electronic IC circuit design, CMOS devices can simplify circuit design, improve safety capability, and reduce power consumption. However, the congenital two-dimensional election gas channel of AlGaN/GaN was usually dominated by D-mode devices, but E-mode devices were still a great challenge to meet the criteria of high-speed, high power and normally-off design. In this study, the gate-recessed region and the gate oxide layer of D-mode MOS-HEMTs were directly etched and were directly grown by using the PEC etching method and the PEC oxide method, respectively. Furthermore, E-mode MOSHEMTs were first accomplished by using photoelectrochemical (PEC) etched gate-recessed structure. Furthermore, a LiNbO3 ferroelectric gate oxide layer and Al2O3/HfO2/LiNbO3 ferroelectric gate stacked oxide layers were deposited on the AlGaN/GaN structure, respectively. To form the monolithic CMOS unskewed inverter, the current ratio of E/D-mode MOSHEMTs was adjusted by changing various etching depths in the AlGaN layer of the load type D-mode transistors. Compared to the conventional tuning method by adjusting the channel width, this etching process method was beneficial to scaling down the chip area of CMOS-HEMTs due to the matching size of the E-mode and D-mode MOSHEMTs. In this research, we demonstrate that as the input signal was 5 V, the output swing of the resulting CMOS-HEMTs with the E/D-mode transistor current ratio (β) of 22 was 4.9 V. The noise margin high and low were about 1.99 V and 1.73 V, respectively. As to the voltage transfer curve (VTC), the corresponded VIN about 2.5 V was closer to VDD/2 (= 2.5 V) as the VOUT was 2.49 V, which revealed that the resulting CMOS-HEMTs with the β of 22 could be operated as an unskewed inverter.
Ching-Ting Lee received his B.S. and M.S. degrees in the Electrical Engineering Department of the National Cheng Kung University, Taiwan, in 1972 and 1974, respectively. He received his Ph.D. degree from the Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982. He joined on National Cheng Kung University as the Dean of the College of Electrical Engineering and Computer Science from 2003 to 2009, and was the chair professor at the Institute of Microelectronics, Department of Electrical Engineering of the National Cheng Kung University. He joined on Yuan Ze University as the vice president from 2018 to 2022, and now he is the chair professor in Yuan Ze University. Among the awards and honors, he has received are Fellow of IEEE and Fellow of IET, Asia-Pacific Academy Fellow, International Association of Advanced Materials Fellow in Sweden, the Outstanding Research Professor Fellowship from the National Science Council (NSC), Engineering Medal from the Electrical engineering Society, distinguish service award from Institute of Electrical Engineering Society, the Optical Engineering Medal from Optical Engineering Society, Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society, and Distinguish Engineering professor award from the Chinese Institute of Engineers. He received the ASIA’s Education Excellence Awards from Singapore, International Association of Advanced Materials (IAAM) Fellow from Sweden, and Chair Professor of National Research Council from Canada. His research activities have also investigated III-V semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits.
Dr. Michael Shebanow (CTO of SAPEON Inc.)
“The Ocean of Compute”
Computing implementation technology has provided an “ocean of compute” at our disposal. Data centers with millions of cores, exaflops of math, petabytes of high-speed DRAM, and exabytes per second of memory bandwidth are now possible. With those capabilities comes problems of cost, both in capital equipment and in the energy needed to power such centers. However, and perhaps equally challenging, are problems of writing software to control and take advantage of such capability. We need a new programming paradigm, one that makes it easier to leverage the immense capability of future computing centers.
Michael Shebanow is currently CTO at Sapeon, a startup developing AI inference accelerators for the cloud. Michael received his Ph.D. from UC Berkeley in Computer Architecture, focusing on high performance computer architecture. He then worked at several companies developing high performance, out-of-order superscalar CPUs (Motorola, HaL, Cyrix, AMD). After that, he worked at NVIDIA on several GPUs (G80, Fermi) and project Denver (CPU) as well as NV Research. After NVIDIA, he joined Samsung where he helped build a team developing Samsung’s first mobile GPU. After Samsung, he joined Cadence where he was VP Of Engineering of the Tensilica group. After leaving Cadence, Michael joined Silicon Catalyst as an advisor to several startups, finally joining member company AlphaICs as its CTO. After leaving AlphaICs, he joined Sapeon. Michael is an IEEE Fellow.
